It is well known that a double-gate MOSFET has several advantages over a conventional single-gate MOSFET: higher transconductance, lower parasitic capacitance, and better short-channel effects. Monte-Carlo simulation has been carried out on a 30 nm channel double-gate MOSFET, which shows very high transconductance (2300 mS/mm) and fast switching speed (1.1 ps for nMOSFET). Moreover, good short-channel characteristics are obtained down to 20 nm channel length with no doping needed in the channel region. This circumvents all the tunneling breakdown, dopant quantization, and dopant depletion problems associated with channel doping.
However, there is no satisfactory way of making such a double-gate structure with both top and bottom gates self-aligned to the channel region. Previous efforts on fabricating double-gate MOSFET's generally fall into one of the following three categories:
(a) Etch silicon into a pillar structure and deposit gates around it. PA1 (b) Make a conventional single-gate MOSFET, then use either selective epitaxy or bond-and-etch-back techniques and form the second gate. PA1 (c) Start with a thin SOI film, pattern a strip and dig a tunnel across it by etching the buried oxide. Then deposit gate electrodes in the tunnel and on top of the SOI film.
There are serious drawbacks in all of the above approaches. For example, in (a), it is difficult to form a vertical pillar as thin as 10 nm with good thickness control and free of RIE damage. In (b), it is difficult to keep the top and bottom gate oxides at the same thickness and to have the gates self-aligned to each other. And again, in (c), thickness control and top/bottom gate self-alignment are major problems.
Thus, it can be seen that a need has arisen for a method of fabricating a double-gated MOSFET which avoids the foregoing shortcomings of the prior art.